1. Field of the Invention
The present invention relates generally to a fabrication process of a semiconductor device. More specifically, the invention relates to a heat treatment method utilizing a furnace.
2. Description of the Related Art
FIG. 1 shows a section of an NPN type bipolar transistor. As shown in FIG. 1, in the NPN type bipolar transistor, a P-type base region 52 is selectively formed in an N-type epitaxial layer 51 which serves as a collector region, and an insulation layer 53 of a silicon dioxide is formed on the P-type base layer 52.
In the silicon dioxide layer 53, an emitter window 54 is selectively formed at a portion above the P-type base region 52. A polycrystalline silicon electrode 55 is selectively formed to be buried within the emitter hole 54. Subsequently, an N-type impurity, such as arsenic or so forth, is doped in the polycrystalline silicon electrode 55. Then, heat treatment is performed for selectively forming an N-type emitter region 57 on the surface of the P-type base region 52.
The formation process of the polycrystalline silicon electrode 55 is performed by way of a low pressure chemical vapor deposition method. In the process of formation, a silicon dioxide layer 56 normally in a thickness of 15 to 30 .ANG., which is referred to as natural oxide layer, is formed between the polycrystalline silicon electrode 55 and the P-type base region 52.
Depending upon the thickness of the natural oxide layer 56, a common-emitter current gain h.sub.FE (hereinafter occasionally expressed only by "h.sub.FE ") is determined. Therefore, in the fabrication process of the bipolar transistor, it becomes necessary to have high controllability of the low pressure chemical vapor deposition and thus controllability of h.sub.FE.
FIG. 2 is a section of a heat treatment apparatus employed in a conventional fabrication process for a semiconductor device, and shows a construction of a heat treatment furnace employed in a process for forming the polycrystalline silicon electrode 55 in the conventional semiconductor device (see Japanese Unexamined Patent Publication (Kokai) No. Showa 59-35433). As shown in FIG. 2, in the conventional heat treatment furnace, a furnace tube 2 is inserted within the furnace body 1 in horizontal orientation. The furnace tube 2 is formed into a cylindrical configuration and has an end wall 8 at one end and an opening 9 for inserting and removing a boat 4 into and out of the furnace tube 2 at the other end. The opening 9 is closed by a lid 10. On the end wall 8 of the furnace tube 2, a vacuum pump 5 is provided for ventilating the furnace tube 2 to establish a vacuum condition therein. Also, in the end wall 8 of the furnace tube 2, a gas introduction port 6 for introducing an inert gas, such as N.sub.2 gas, is provided. In the lid 10, a material gas introduction port 7 for introducing a material gas is provided. The furnace tube 2 is designed to accommodate the boat 4, on which a plurality of semiconductor wafers 3 are arranged vertically with a given interval.
In the conventional heat treatment apparatus, when the semiconductor wafers 3 are inserted into the furnace tube 2, an N.sub.2 gas is flowed within the furnace tube 2 via an introduction port 6 for preventing ambient air from penetrating into the interior space of the furnace tube 2 and thus for preventing fluctuation of the quality of the product due to disturbance of atmosphere in the furnace tube 2.
It should be noted that the penetration of the ambient air means that the ambient air is introduced into the interior space of the furnace tube 2 together with the semiconductor wafer 3 upon insertion of the semiconductor wafers 3 into the furnace tube 2.
Next, conventional process steps will be discussed.
In general, in the low pressure chemical vapor deposition method of a polycrystalline silicon, the semiconductor wafers 3 and the boat 4 are inserted into the furnace tube 2 under a flow of N.sub.2 gas within the interior space of the furnace tube 2. Subsequently, the gas in the furnace tube 2 is discharged by means of the vacuum pump 5 to establish a vacuum condition (approximately 0.75 Torr). Thereafter, by introducing a silane gas as the material gas through the introduction port 7, a polycrystalline silicon layer is grown on the surface of the semiconductor wafer 3. Subsequently, N.sub.2 gas is introduced into the interior space of the furnace tube 2 through the introduction port 6 for purging. Thereafter, with maintaining supply of the N.sub.2 gas into the furnace tube 2, the lid 10 is opened to remove the semiconductor wafers 3 from the furnace tube 2.
To avoid the influence of a small amount of oxygen brought into the furnace tube with the semiconductor wafers 3, according to a further known method the semiconductor wafers 3 are inserted into the furnace tube 2 while maintaining a temperature in the furnace at low temperature. A vacuum condition is then established within the furnace, the interior space of the furnace is purged by introduction of the N.sub.2 gas, and thereafter the temperature within the furnace is elevated to perform heat treatment. Such method has been disclosed in Japanese Unexamined Patent Publication No. Showa 59-35433. On the other hand, Japanese Unexamined Patent Publication No. Heisei 2-20328 discloses a method for performing heat treatment by providing a preliminary vacuum chamber at the opening portion of the furnace tube, and initially placing the wafer boat holding the semiconductor wafers within the preliminary vacuum chamber, subsequently introducing inert gas into the preliminary vacuum chamber for replacing the atmosphere in the preliminary vacuum chamber with the inert gas, and then transferring the boat holding the semiconductor wafers from the preliminary vacuum chamber to the furnace tube to perform heat treatment.
However, in the conventional heat treatment apparatus for the semiconductor device, a problem is encountered in that a larger diameter furnace tube 2 inherently has a higher possibility of introduction of the ambient air into the furnace tube 2 upon insertion of the boat 4 supporting the semiconductor wafers 3.
In addition, because of non-uniformity of heat distribution within the furnace, a condition for heat treatment for the semiconductor wafers 3 can be fluctuate depending upon the position of respective semiconductor wafers 3 within the boat 4.
For instance, when a polycrystalline silicon layer for the emitter electrode is to be grown by the low pressure chemical vapor deposition method, due to penetration of ambient air into the furnace tube and non-uniformity of the temperature distribution to the furnace, the natural oxide layer formed at the emitter contact portion may have relatively large local fluctuation in thickness in a respective wafer, fluctuation in thickness between a plurality of wafers and fluctuation in thickness between batch processes. The polycrystalline silicon layer comprising the emitter electrode is formed on the natural oxide layer having large fluctuation as set forth above. As a result, fluctuation in h.sub.FE of the bipolar transistor is caused and a yield of production is lowered.
Moreover even in the method for preventing penetration of ambient air by inserting the semiconductor wafers after maintaining a low temperature in the furnace, since heat treatment is performed after inserting the semiconductor wafers at low temperature, it requires a long process period or makes the apparatus large.
Furthermore, even by the method of providing the preliminary vacuum chamber and placing the semiconductor wafers within the inert gas atmosphere within the preliminary vacuum chamber and then transferring the semiconductor wafers into the furnace tube, the process period is similarly expanded and the apparatus is made larger.